Method and apparatus for matching trace lengths of signal lines making 90°/180° turns

ABSTRACT

A printed circuit board (PCB) includes a first 90° signal line. The first 90° signal line connects a first location on a first layer of the PCB to a second location on a second layer of the PCB. The PCB includes a second 90° signal line. The second 90° signal line is adjacent and equal in length to the first 90° signal line. The second 90° signal line connects a third location on the first layer of the PCB to a fourth location on the second layer of the PCB.

FIELD OF THE INVENTION

The present invention relates to signal line routing on a printedcircuit board. More specifically, the present invention relates to amethod and apparatus for matching trace lengths of signal lines making90° and 180° turns on a printed circuit board.

BACKGROUND OF THE INVENTION

Computer systems often include devices that are positioned on a printedcircuit board such that signal lines interfacing the devices arerequired to make 90° or 180° turns. FIG. 1 illustrates an example of aprior art technique for routing signal lines making 90° degree turns.FIG. 1 shows a printed circuit board 100 having an electrical connector110 that interfaces with an off-board component (not shown). Device 120is mounted on the printed circuit board 100 and includes contacts (notshown) that interface with land pads 125-127 on the printed circuitboard 100. The electrical connector 110 receives off-board signals thatare transmitted to the land pads 125-127. The signals must be routed onsignal lines making a 90° turn from the electrical connector 110 to theland pads 125-127.

Signal lines 130, 140, and 150 route signals from the electricalconnector 110 to the land pads 125-127. The signal line 130 includes afirst section 131 on a first layer 160 of the printed circuit board 100that connects a first location on the electrical connector 110 to afirst via 135 on the first layer 160 of the printed circuit board 100.The signal line 130 includes a second section 132 on a second layer (notshown) of the printed circuit board 100 that connects the first via 135to the land pad 127. The signal line 140 includes a first section 141 onthe first layer 160 of the printed circuit board 100 that connects asecond location on the electrical connector 110 to a second via 145 onthe first layer 160 of the printed circuit board 100. The signal line140 includes a second section 142 on the second layer of the printedcircuit board 100 that connects the second via 145 to the land pad 126.The signal line 150 includes a first section 151 on the first layer 160of the printed circuit board 100 that connects a third location on theelectrical connector 110 to a third via 155 on the first layer 160 ofthe printed circuit board 100. The signal line 150 includes a secondsection 152 on the second layer of the printed circuit board 100 thatconnects the third via 155 to the land pad 125.

In the past when two layers of a printed circuit board were used forrouting 90° signal lines, the signal lines were routed one direction ona first layer and would make a 90° turn at via "T" points on the secondlayer. The vias were typically packed close together to minimize theamount of space the signal lines would occupy on the printed circuitboard. The vias would be placed without taking into consideration theiraffect on the length of their corresponding signal line. As a result, asillustrated in FIG. 1, the length of the signal lines 130, 140, and 150would differ in length. The length of a signal line affects theelectrical delay and capacitance on the signal line. Differences inelectrical delay and capacitance between signal lines may adverselyeffect the performance of devices connected to the signal lines thatoperate at high speeds.

SUMMARY

A printed circuit board (PCB) is disclosed. The PCB includes a first 90°signal line. The first 90° signal line connects a first location on afirst layer of the PCB to a second location on a second layer of thePCB. The PCB includes a second 90° signal line. The second 90° signalline is adjacent and equal in length to the first 90° signal line. Thesecond 90° signal line connects a third location on the first layer ofthe PCB to a fourth location on the second layer of the PCB.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not by way oflimitation in the figures of the accompanying drawings, in which thelike references indicate similar elements in and in which:

FIG. 1 illustrates a prior art routing techniques for routing signallines making 90° turns on a printed circuit board;

FIG. 2 is a block diagram of a computer system implementing anembodiment of the present invention;

FIG. 3 illustrates a memory system mounted on a motherboard according toan embodiment of the present invention;

FIG. 4 illustrates an exemplary memory module according to an embodimentof the present invention;

FIG. 5 illustrates an exemplary technique for routing signal linesmaking 90° turns on a printed circuit board utilizing two layers of theprinted circuit board according to an embodiment of the presentinvention;

FIG. 6 illustrates an exemplary technique for routing signal linesmaking 90° turns on a printed circuit board utilizing four layers of theprinted circuit board according to an embodiment of the presentinvention;

FIG. 7 illustrates an exemplary technique for routing signal linesmaking 180° turns on a printed circuit board utilizing four layers ofthe printed circuit board according to an embodiment of the presentinvention; and

FIG. 8 is a flow chart illustrating a method for routing signalsaccording to an embodiment of the present invention.

DETAILED DESCRIPTION

FIG. 2 illustrates a computer system upon which an embodiment of thepresent invention can be implemented is shown as 200. The computersystem 200 includes a processor 201 that processes data signals. Theprocessor 201 may be a complex instruction set computer (CISC)microprocessor, a reduced instruction set computing (RISC)microprocessor, a very long instruction word (VLIW) microprocessor, aprocessor implementing a combination of instruction sets, or otherprocessor device. FIG. 2 shows an example of the present inventionimplemented on a single processor computer system 200. However, it isunderstood that the present invention may be implemented in a computersystem having multiple processors. The processor 201 is coupled to a CPUbus 210 that transmits data signals between processor 201 and othercomponents in the computer system 200.

The computer system 200 includes a memory 213. The memory 213 may be adynamic random access memory (DRAM) device, a synchronous dynamic randomaccess memory (SDRAM) device, or other memory device. The memory 213 maystore instructions and code represented by data signals that may beexecuted by the processor 201. According to an embodiment of thecomputer system 200, the memory 213 comprises a memory system having aplurality of memory modules. Each of the memory modules comprises aprinted circuit board having a plurality of memory devices mounted onthe printed circuit board. The printed circuit board operates as adaughter card insertable into a socket connector that is connected tothe computer system 200.

A bridge memory controller 211 is coupled to the CPU bus 210 and thememory 213. The bridge memory controller 211 directs data signalsbetween the processor 201, the memory 213, and other components in thecomputer system 200 and bridges the data signals between the CPU bus210, the memory 213, and a first I/O bus 220.

The first I/O bus 220 may be a single bus or a combination of multiplebuses. As an example, the first I/O bus 220 may comprise a PeripheralComponent Interconnect (PCI) bus, a Personal Computer Memory CardInternational Association (PCMCIA) bus, a NuBus, or other buses. Thefirst I/O bus 220 provides communication links between components in thecomputer system 200. A network controller 221 is coupled to the firstI/O bus 220. The network controller 221 links the computer system 200 toa network of computers (not shown in FIG. 2) and supports communicationamong the machines. A display device controller 222 is coupled to thefirst I/O bus 220. The display device controller 222 allows coupling ofa display device to the computer system 200 and acts as an interfacebetween the display device and the computer system 200. The displaydevice controller may be a monochrome display adapter (MDA) card, acolor graphics adapter (CGA) card, an enhanced graphics adapter (EGA)card, an extended graphics array (XGA) card or other display devicecontroller. The display device may be a television set, a computermonitor, a flat panel display or other display device. The displaydevice receives data signals from the processor 201 through the displaydevice controller 222 and displays the information and data signals tothe user of the computer system 200. A video camera 223 is coupled tothe first I/O bus 220.

A second I/O bus 230 may be a single bus or a combination of multiplebuses. As an example, the second I/O bus 230 may comprise a PCI bus, aPCMCIA bus, a NuBus, an Industry Standard Architecture (ISA) bus, orother buses. The second I/O bus 230 provides communication links betweencomponents in the computer system 200. A data storage device 231 iscoupled to the second I/O bus 230. The data storage device 231 may be ahard disk drive, a floppy disk drive, a CD-ROM device, a flash memorydevice or other mass storage device. A keyboard interface 232 is coupledto the second I/O bus 230. The keyboard interface 232 may be a keyboardcontroller or other keyboard interface. The keyboard interface 232 maybe a dedicated device or can reside in another device such as a buscontroller or other controller. The keyboard interface 232 allowscoupling of a keyboard to the computer system 200 and transmits datasignals from a keyboard to the computer system 200. An audio controller233 is coupled to the second I/O bus 230. The audio controller 233operates to coordinate the recording and playing of sounds is alsocoupled to the I/O bus 230.

A bus bridge 224 couples the first I/O bus 220 to the second I/O bus230. The bus bridge 224 operates to buffer and bridge data signalsbetween the first I/O bus 220 and the second I/O bus 230.

FIG. 3 illustrates a memory system 213 according to an embodiment of thepresent invention. The memory system 213 resides on a motherboard 300 ofthe computer system 200 (shown in FIG. 2). The motherboard 300 is aprinted circuit board that interconnects components of the computersystem 200 such as the bridge memory controller 211, the processor 201and other components. The memory system 213 includes a plurality ofmemory modules 310-312. Each of the memory modules includes a pluralityof memory devices mounted on the memory module. The memory system alsoincludes a plurality of socket connectors 320-322 mounted on themotherboard 300. The memory modules 310-312 are insertable into thesocket connectors 320-322. Electrical connectors on the memory moduleinterface with electrical contacts in the socket connector. Theelectrical connectors and the electrical contacts allow components onthe motherboard 300 to access the memory devices on the memory module.It should be appreciated that any number of socket connectors may bemounted on the motherboard to receive any number of memory modules. Itshould also be appreciated that any number of memory devices may bemounted on each memory module.

FIG. 4 illustrates an exemplary memory module 310 according to anembodiment of the present invention. The memory module 310 includes aplurality of memory devices 420-427 on the memory module 310. The memorydevice 420 includes a plurality of contacts (not shown) that interfacewith land pads 480-484 on the memory module 310. Memory devices 421-427also include a plurality of contacts that interface with land pads onthe memory module 310 but are not shown in FIG. 4. According to anembodiment of the present invention, the memory devices 420-427 areSDRAM devices. It should be appreciated that any type of memory devicesmay be mounted on the memory module 310. The memory devices 420-427 maybe packaged in a ball grid array (BGA), chip scale package (CSP), orother type of packaging.

The memory module 310 includes an electrical connector 410 that operatesto receive signals from and transmit signals to the bridge memorycontroller 211 (shown in FIG. 2). According to an embodiment of thepresent invention, the electrical connector 410 receives address, data,control, and clock signals from the memory controller 211. A pluralityof signal lines 430, 440, 450, 460, and 470 are coupled to theelectrical connector 410. The signal lines 430, 440, 450, 460, and 470operate to transmit signals from the electrical connector 410 to landpads 480-484 on the memory device 420. The signal lines 430, 440, 450,460, and 470 make a 90° turn from the electrical connector 410 to theland pads 480-484. According to an embodiment of the present invention,the signal lines 430, 440, 450, 460, and 470 are routed through twolayers of the printed circuit board of the memory module 310. The signallines 430, 440, 450, 460, and 470 are equal in length in that the signallines are substantially equal in physical length within a predeterminedtolerance under current manufacturing capabilities that yieldunmeasurable and/or insignificant differences in electricalcharacteristics.

FIG. 5 illustrates an exemplary technique for routing signal linesmaking 90° turns on a printed circuit board utilizing two layers of theprinted circuit board according to an embodiment of the presentinvention. The signal line 430 includes a first trace 531 on a firstlayer 510 of the memory module 310 that connects a first location 511 onthe electrical connector 410 to a first via 535 on the first layer 510of the memory module 310. The signal line 430 includes a second trace532 on a second layer (not shown) of the memory module 310 that connectsthe first via 535 to the land pad 480. The signal line 440 includes afirst trace 541 on the first layer 510 of the memory module 310 thatconnects a second location 512 on the electrical connector 410 to asecond via 545 on the first layer 510 of the memory module 310. Thesignal line 440 includes a second trace 542 on the second layer of thememory module 310 that connects the second via 545 to the land pad 481.The signal line 450 includes a first trace 551 on the first layer 510 ofthe memory module 310 that connects a third location 513 on theelectrical connector 410 to a third via 555 on the first layer 510 ofthe memory module 310. The signal line 450 includes a second trace 552on the second layer of the memory module 310 that connects the third via555 to the land pad 482. The signal line 460 includes a first trace 561on the first layer 510 of the memory module 310 that connects a fourthlocation 514 on the electrical connector 410 to a fourth via 565 on thefirst layer 510 of the memory module 310. The signal line 460 includes asecond trace 562 on the second layer of the memory module 310 thatconnects the fourth via 565 to the land pad 483. The signal line 470includes a first trace 571 on the first layer 510 of the memory module310 that connects a fifth location 515 on the electrical connector 410to a fifth via 575 on the first layer 510 of the memory module 310. Thesignal line 470 includes a second trace 572 on the second layer of thememory module 310 that connects the fifth via 575 to the land pad 484.

The signal lines 430, 440, 450, 460, and 470 are routed such that theyare equal in length. This is achieved by selecting a signal line lengthand strategically placing the vias 535, 545, 555, 565, and 575 at alocation on the memory module 310 such that signal lines routing throughthe vias 535, 545, 555, 565, and 575 would equal that signal linelength. According to an embodiment of the present invention, some of thevias are placed at locations on the memory module 310 which wouldrequire a section of a second trace on a second layer to double backtowards a direction previously traveled by a section of a first trace ona first layer. Thus, when a signal line connecting a land pad and alocation on the electrical connector 410 is shorter in length than theselected signal line length, a via corresponding to the signal line maybe strategically moved to lengthen the traces on the signal line so thatthe length of the signal line matches the selected signal line length.

According to an embodiment of the present invention, when a section of asecond trace doubles back towards a direction previously traveled by asection of a first trace, the section of the second trace may or may notdirectly retrace a path taken by a section of the first trace. Signalline 430 includes a first trace 531 having a first section 533 that isdoubled back by a second section 534 of a second trace 532. A portion ofthe second section 534 retraces a path taken by a portion of the firstsection 533. Signal line 440 includes a first trace 541 having a firstsection 543 that is doubled back by a second section 544 of a secondtrace 542. A portion of the second section 544 also retraces a pathtaken by a portion of the first section 543. Signal line 450 includes afirst trace 551 having a first section 553 that is doubled back by asecond section 554 of a second trace 552. The second section 554 doesnot retrace a path taken by the first section 553. Signal line 460includes a first trace 561 having a first section 563 that is doubledback by a second section 564 of a second trace 562. The second section564 does not retrace a path taken by the first section 563.

FIG. 6 illustrates an exemplary technique for routing signal linesmaking 90° turns on a printed circuit board utilizing four layers of aprinted circuit board according to an embodiment of the presentinvention. FIG. 6 illustrates a memory module 311 having a memory device620 mounted on. The memory device 620 includes a plurality of contacts(not shown) that interface with land pads 480-484 on the memory module311 similarly to the memory device 420. The memory device 620 includesan additional plurality of contacts (not shown) that interface with landpads 680-684 on the memory module 311. The memory module 311 includes aplurality of signal lines 430, 440, 450, 460, and 470 that are equal inlength and that connect locations on the electrical connector 410 toland pads 480-484 similarly to the memory module 310. The memory module311 includes an additional plurality of signal lines 630, 640, 650, 660,and 670 that connect additional locations on the electrical connector410 to the land pads 680-684. The signal lines 630, 640, 650, 660, and670 are routed on a third layer (not shown) and a fourth layer (notshown) of the memory module 311.

The signal line 630 includes a first trace 631 on a third layer (notshown) of the memory module 311 that connects a sixth location 611 onthe electrical connector 410 to a sixth via 635 on the third layer ofthe memory module 311. The signal line 630 includes a second trace 632on a fourth layer of the memory module 311 that connects the sixth via635 to the land pad 680. The signal line 640 includes a first trace 641on the third layer of the memory module 311 that connects a seventhlocation 612 on the electrical connector 410 to a seventh via 645 on thethird layer of the memory module 311. The signal line 640 includes asecond trace 642 on the fourth layer of the memory module 311 thatconnects the seventh via 645 to the land pad 681. The signal line 650includes a first trace 651 on the third layer of the memory module 311that connects a eighth location 613 on the electrical connector 410 to aeighth via 655 on the third layer of the memory module 311. The signalline 650 includes a second trace 652 on the fourth layer of the memorymodule 311 that connects the eighth via 655 to the land pad 682. Thesignal line 660 includes a first trace 661 on the third layer of thememory module 311 that connects a ninth location 614 on the electricalconnector 410 to a ninth via 665 on the third layer of the memory module311. The signal line 660 includes a second trace 662 on the fourth layerof the memory module 311 that connects the ninth via 665 to the land pad683. The signal line 670 includes a first trace 671 on the third layerof the memory module 311 that connects a tenth location 615 on theelectrical connector 410 to a tenth via 675 on the third layer of thememory module 311. The signal line 670 includes a second trace 672 onthe fourth layer of the memory module 311 that connects the tenth via675 to the land pad 684.

As illustrated in FIG. 6, the signal lines 630, 640, 650, 660, and 670are routed similarly to signal lines 430, 440, 450, 460, and 470 in thatthey are routed such that they are equal in length. This is achieved byselecting a signal line length and strategically placing the vias 635,645, 655, 665, and 675 at locations on the memory module 311 such thatsignal lines routing through the vias 635, 645, 655, 665, and 675 wouldequal that signal line length. According to an embodiment of the presentinvention, some of the vias are placed at a location on the memorymodule 311 which would require a section of a second trace on one layerto double back towards a direction previously traveled by a section of afirst trace on a second layer. By utilizing a third and fourth layer ofthe memory module 311, a portion of the signal lines 630, 640, 650, 660,and 670 may be routed above or underneath signal lines 430, 440, 450,460, and 470 thus conserving surface area on the memory module 311.Utilizing an additional two layers of the memory module 311 to route 90°signal lines allows twice as many signal lines to be routed in the sameamount of space.

FIG. 7 illustrates an exemplary technique for routing signal linesmaking 180° turns on a printed circuit board utilizing four layers ofthe printed circuit board according to an embodiment of the presentinvention. FIG. 7 illustrates the memory module 312 having a firstmemory device 710 and a second memory device 720. The first memorydevice 710 includes a plurality of contacts (not shown) that interfacewith land pads 711-716 on the memory module 312. The second memorydevice 720 includes a plurality of contacts (not shown) that interfacewith land pads 721-726 on the memory module 312. The memory module 312includes a plurality of signal lines 730, 740, 750, 760, 770, and 780that connect the land pads 711-716 interfacing the first memory device710 with the land pads 721-726 interfacing the second memory device 720.The memory devices 710 and 720 are configured on the memory module 312such that the signal lines 730, 740, 750, 760, 770, and 780 must berouted to make a 180° turn in order to connect the land pads 711-716 tothe land pads 721-726.

The signal line 730 includes a first trace 731 on a first layer 700 ofthe memory module 312 that connects the land pad 711 to a first via 732on the first layer 700 of the memory module 312. The signal line 730includes a second trace 733 on a second layer (not shown) of the memorymodule 312 that connects the first via 732 to a second via 734 on thesecond layer of the memory module 312. The signal line 730 includes athird trace 735 on the first layer 700 of the memory module 310 thatconnects the second via 734 to the land pad 721 on the first layer 700of the memory module 312.

The signal line 740 includes a first trace 741 on a third layer (notshown) of the memory module 312 that connects the land pad 712 to athird via 742 on the third layer of the memory module 312. The signalline 740 includes a second trace 743 on a fourth layer (not shown) ofthe memory module 312 that connects the third via 742 to a fourth via744 on the fourth layer of the memory module 312. The signal line 740includes a third trace 745 on the third layer of the memory module 312that connects the fourth via 744 to the land pad 722 on the third layerof the memory module 312. By routing the signal line 740 through thethird and fourth layers of the memory module 312, portions of the signalline 740 may be routed above or beneath the signal line 750 asillustrated in FIG. 7. This allows surface area on the memory module 312to be conserved while increasing signal line routing density.

The signal line 750 includes a first trace 751 on a first layer 700 ofthe memory module 312 that connects the land pad 713 to a fifth via 752on the first layer 700 of the memory module 312. The signal line 750includes a second trace 753 on a second layer (not shown) of the memorymodule 312 that connects the fifth via 752 to a sixth via 754 on thesecond layer of the memory module 312. The signal line 750 includes athird trace 755 on the first layer 700 of the memory module 312 thatconnects the sixth via 754 to the land pad 723 on the first layer 700 ofthe memory module 312.

The signal line 760 includes a first trace 761 on a third layer of thememory module 312 that connects the land pad 714 to a seventh via 762 onthe third layer of the memory module 312. The signal line 760 includes asecond trace 763 on the fourth layer of the memory module 312 thatconnects the seventh via 762 to a eighth via 764 on the fourth layer ofthe memory module 312. The signal line 760 includes a third trace 765 onthe third layer of the memory module 312 that connects the eighth via764 to the land pad 724 on the third layer of the memory module 312. Byrouting the signal line 760 through the third and fourth layers of thememory module 312, portions of the signal line 760 may be routed aboveor beneath the signal line 770 as illustrated in FIG. 7. This allowssurface area on the memory module 312 to be conserved while increasingsignal line routing density.

The signal line 770 includes a first trace 771 on a first layer 700 ofthe memory module 312 that connects the land pad 715 to a ninth via 772on the first layer 700 of the memory module 312. The signal line 770includes a second trace 773 on a second layer of the memory module 312that connects the ninth via 772 to a tenth via 774 on the second layerof the memory module 312. The signal line 770 includes a third trace 775on the first layer 700 of the memory module 312 that connects the tenthvia 774 to the land pad 725 on the first layer 700 of the memory module312.

The signal line 780 includes a first trace 781 on a third layer of thememory module 312 that connects the land pad 716 to an eleventh via 782on the third layer of the memory module 312. The signal line 780includes a second trace 783 on a fourth layer of the memory module 312that connects the eleventh via 782 to a twelfth via 784 on the fourthlayer of the memory module 312. The signal line 780 includes a thirdtrace 785 on the third layer of the memory module 312 that connects thetwelfth via 784 to the land pad 726 on the third layer of the memorymodule 312.

The signal lines 730, 740, 750, 760, 770, and 780 are routed such thatthey are equal in length. This is achieved by selecting a signal linelength and strategically placing the vias 732, 734, 742, 744, 752, 754,762, 764, 772, 774, 782, and 784 at locations on the memory module 312such that signal lines routing through them would equal that signal linelength. According to an embodiment of the present invention, some of thevias are placed at a location on the memory module 312 which wouldrequire a section of a second trace on a first layer to double backtowards a direction previously traveled by a section of a first trace ona second layer. According to an embodiment of the present invention,some of the vias are placed at a location on the memory module 312 whichwould require a section of a fourth trace on one layer to double backtowards a direction previously traveled by a section of a third trace ona second layer. Thus, when a signal line connecting a first land pad anda second land pad is shorter in length than the selected signal linelength, vias corresponding to the signal line may be strategically movedto lengthen the traces on the signal line so that the length of thesignal line matches the selected signal line length. It should beappreciated that two layers and one row of vias may also be used to makea 180° turn.

The routing techniques of the present invention is disclosed as beingimplemented on the memory system 213 (shown in FIG. 3). It should beappreciated that the routing techniques of the present invention may beimplemented on any type of application requiring signal lines to make90° or 180° turns. The signal lines may be used to connect contacts,land pads, electrical connectors or any other electrical connection onany layer of a printed circuit board.

FIG. 8 is a flow chart illustrating a method for routing signalsaccording to an embodiment of the present invention. At step 801, asignal line length is determined. According to an embodiment of thepresent invention, the signal line length may be determined byestimating a maximum distance between two locations that require asignal line connection.

At step 802, a first signal line is routed 90°'s from a first locationon a printed circuit board to a second location on the printed circuitboard. According to an embodiment of the present invention, the firstlocation is on a first layer of the printed circuit board and the secondlocation is on a second layer of the printed circuit board. The firstsignal line is routed from the first location to a first via on thefirst layer of the printed circuit board. The first signal line isrouted from the first via to the second location on the second layer ofthe printed circuit board.

At step 803, a second signal line is routed 90°'s from a third locationon the printed circuit board to a fourth location on the printed circuitboard while matching the length of the second signal line with the firstsignal line. According to an embodiment of the present invention, thethird location is on the first layer of the printed circuit board andfourth location is on a second layer of the printed circuit board. Thesecond signal line is routed from the third location to a second via onthe first layer of the printed circuit board. The second signal line isrouted from the second via to the fourth location on the second layer ofthe printed circuit board. According to an alternate embodiment of thepresent invention, the third location is on a third layer of the printedcircuit board and the fourth location is on a fourth layer of theprinted circuit board. The second signal line is routed from the thirdlocation to a second via on the third layer of the printed circuitboard. The second signal line is routed from the second via to thefourth location on the fourth layer of the printed circuit board.

The length of the second signal line is matched with the first signalline by selecting a placement of the first and second vias such that asum of the length of a first trace connecting the first location and thefirst via and the length of a second trace connecting the first via andthe second location match that of a sum of the length of a third traceconnecting the third location and the second via and the length of afourth trace connecting the second via to the fourth location. Accordingto an embodiment of the present invention, the placement of the firstand second vias causes a section of the second and fourth traces todouble back in a direction traveled by a section of the first and thirdtraces.

In the foregoing description, the invention is described with referenceto specific exemplary embodiments thereof. It will, however, be evidentthat various modifications and changes may be made thereto withoutdeparting from the broader spirit and scope of the present invention asset forth in the appended claims. The specification and drawings are,accordingly to be regarded in an illustrative rather than a restrictivesense.

What is claimed is:
 1. A method for routing signals on a printed circuitboard (PCB), comprising:routing a first signal line 90°'s from a firstlocation on a first layer of the PCB to a second location on a secondlayer of the PCB; routing a second signal line, adjacent to the firstsignal line, 90°'s from a third location on the first layer of the PCBto a fourth location on the second layer of the PCB while matching thelength of the second signal line with the first signal line.
 2. Themethod of claim 1, wherein routing the first signal line,comprises:routing the first signal line from the first location to afirst via on the first layer of the PCB; and routing the first signalline from the first via to the second location on the second layer ofthe PCB.
 3. The method of claim 1, wherein routing the second signalline, comprises:routing the second signal line from the third locationto a second via on the first layer of the PCB; and routing the secondsignal line from the second via to the fourth location on the secondlayer of the PCB.
 4. The method of claim 3, wherein matching the lengthof the second signal line with the first signal linecomprises:determining a signal line length; and selecting a placement ofthe first and second vias such that a sum of a length of a first traceconnecting the first location and the first via and a length of a secondtrace connecting the first via and the second location match that of asum of a length of a third trace connecting the third location and thesecond via and a length of a fourth trace connecting the second via andthe fourth location.
 5. The method of claim 4, wherein the placement ofthe second via causes a section of the fourth trace to double back in adirection traveled by a section of the third trace.
 6. A method forrouting signals on a printed circuit board (PCB), comprising:routing afirst signal line 90°'s from a first location on a first layer of thePCB to a second location on a second layer of the PCB; and routing asecond signal line 90°'s from the third location on a third layer of thePCB to fourth location on a fourth layer of the PCB while matching thelength of the second signal line with the first signal line.
 7. Themethod of claim 6, wherein routing the first signal linecomprises:routing the first signal line from the first location on thePCB to a first via on a first layer of the PCB; and routing the firstsignal line from the first via to a second location on a second layer ofthe PCB.
 8. The method of claim 6, wherein routing the second signalline comprises:routing the second signal line from a third location onthe PCB to a second via on a third layer of the PCB; and routing thesecond signal from the via to the fourth location on the fourth layer ofthe PCB.
 9. The method of claim 8, wherein matching the length of thefirst signal line with the second signal line comprises:determining asignal line length; and selecting a placement of the first and secondvias such that a sum of a length of a first trace connecting the firstlocation and the first via and a length of a second trace connecting thefirst via and the second location match that of a sum of a length of athird trace connecting the third location and the second via and alength of a fourth trace connecting the second via and the fourthlocation.
 10. The method of claim 9, wherein the placement of the secondvia causes a section of the fourth trace to double back in a directiontraveled by a section of the third trace.
 11. A printed circuit board(PCB), comprising:a first 90° signal line that connects a first locationon a first layer of the PCB to a second location on a second layer ofthe PCB; and a second 90° signal line, adjacent and equal in length tothe first 90° signal line, that connects a third location on the firstlayer of the PCB to a fourth location on the second layer of the PCB.12. The PCB board of claim 11, wherein the first 90° signal line,comprises:a first trace that connects the first location to a first viaon the first layer of the PCB; and a second trace that connects thefirst via to the second location on the second layer of the PCB.
 13. ThePCB board of claim 11, wherein the second 90° signal line comprises:athird signal trace that connects the third location to a second via onthe first layer of the PCB; anda fourth trace that connects the secondvia to the fourth location on the second layer of the PC.
 14. A printedcircuit board (PCB), comprising:a first 90° signal line that connects afirst location on a first layer of the PCB to a second location on asecond layer of the PCB; a second 90° signal line, adjacent and equal inlength to the first 90° signal line, that connects a third location on athird layer of the PCB to a fourth location on a fourth layer of thePCB.
 15. The PCB of claim 14, wherein the first 90° signal line,comprises:a first trace that connects the first location to a first viaon the first layer of the PCB; and a second trace that connects thefirst via to the second location on the second layer of the PCB.
 16. ThePC board of claim 14, wherein the second 90° signal line comprises:athird trace that connects the third location to a second via on thethird layer of the PCB; and a fourth trace that connects the second viato a fourth location on the fourth layer of the PCB.
 17. A printedcircuit board (PCB), comprising:a first 180° signal line that connects afirst location on a first layer of the PCB to a second location on thefirst layer of the PCB; a second 180° signal line, adjacent and equal inlength to the first 180° signal line, that connects a third location ona third layer of the PCB to a fourth location on a third layer of thePCB.
 18. The PCB of claim 17, wherein the first 180° signal line,comprises:a first trace on the first layer of the PCB that connects thefirst location to a first via on the first layer of the PCB; a secondtrace on the second layer of the PCB that connects the first via to asecond via on the second layer of the PCB; and a third trace on thefirst layer of the PCB that connects the second via to the secondlocation on the first layer of the PCB.
 19. The PCB of claim 17, whereinthe second 180° signal line comprises:a fourth trace on the third layerof the PCB that connects the third location to a third via on the thirdlayer of the PC board; a fifth trace on the fourth layer of the PCB thatconnects the third via to a fourth via on the fourth layer of the PCB;and a sixth trace on the third layer of the PCB that connects the fourthvia to a fourth location on the third layer of the PCB.
 20. A computersystem, comprising:a bus; a processor coupled to the bus; and a memorysystem, coupled to the bus, that includes a memory module having a first90° signal line that connects a first location on a first layer of thememory module to a second location on a second layer of the memorymodule, and a second 90° signal line, adjacent and equal in length tothe first 90° signal line, that connects a third location on the firstlayer of the memory module to a fourth location on the second layer ofthe memory module.
 21. The computer system of claim 20, wherein thefirst 90° signal line, comprises:a first trace that connects the firstlocation to a first via on the first layer of the memory module; and asecond trace that connects the first via to the second location on thesecond layer of the memory module.
 22. The computer system of claim 20,wherein the second 90° signal line comprises:a third trace that connectsthe third location to a second via on the first layer of the memorymodule; and a fourth trace that connects the second via to a fourthlocation on the second layer of the memory module.